1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, to an improvement of a column selecting system.
2. Description of the Background Art
FIG. 24 is a block diagram showing an example of a dynamic random access memory will be referred to as "DRAM" hereinafter) in the prior art. FIG. 25 specifically shows a structure of a major part of the DRAM shown in FIG. 24.
Four memory blocks are provided on a semiconductor chip CH. However, FIG. 24 shows only one memory block B1 among them.
A memory array 1 includes a plurality of bit line pairs, a plurality of word lines crossing the bit line pairs, and a plurality of memory cells disposed at crossings of the bit line pairs and the word lines. In FIG. 25, there are shown bit line pairs BL1-BL8, a plurality of word lines WL crossing the bit line pairs BL1-BL8, and a plurality of memory cells MC disposed at the crossings of the bit line pairs BL1-BL8 and word lines WL. The bit line pairs are divided into a plurality of bit line groups BG1 and BG2, each of which includes four bit line pairs. In FIG. 25, the bit line pairs BL1-BL4 form the bit line group BG1, and the bit line pairs BL5-BL8 form the bit line group BG2.
The word lines WL are connected to a row decoder 2 shown in FIG. 24. The row decoder 2 selects any one of the word lines WL to activate the selected word line WL. The row decoder 2 sets the potential of the selected word line at a high level, and sets the potential of the unselected word lines at a low level.
A sense amplifier group 3 shown in FIG. 24 includes a plurality of sense amplifiers SA (FIG. 25) which are connected to the bit line pairs, respectively. Each sense amplifier SA senses and amplifies a potential difference on the corresponding bit line pair.
A column selecting circuit group 4 shown in FIG. 24 includes a plurality of column selecting circuits which are provided corresponding to the bit line groups, respectively. In FIG. 25, there are shown a column selecting circuit SL1 provided corresponding to the bit line group BG1, and a column selecting circuit SL2 provided corresponding to the bit line group BG2.
Each column selecting circuit includes four sets of transfer gates TG which correspond to the four bit line pairs in each bit line group, respectively. The four bit line pairs in each bit line group are connected through four sets of the transfer gates TG to four input/output line pairs IO1-IO4, respectively.
A column decoder 5 selects any one of the bit line groups, and renders four sets of the transfer gates TG in the corresponding column selecting circuit conductive simultaneously. In FIG. 25, the column decoder 5 generates a column selecting signal CSL1, which is applied to four sets of the transfer gates TG in the column selecting circuit SL1, and also generates a column selecting signal CSL2, which is applied to four sets of the transfer gates TG in the column selecting circuit SL2.
In FIG. 24, the memory block B1 further includes an input buffer 6, a 4-bit serial/parallel converter circuit 7, a write buffer 8, a preamplifier 9, a 4-bit parallel/serial converter circuit 10 and an output buffer 11. The input buffer 6, serial/parallel converter circuit 7 and write buffer 8 operate in a data write operation. The preamplifier 9, parallel/serial converter circuit 10 and output buffer 11 operate in a data read operation.
On the semiconductor chip CH, there are further provided a row address buffer 12, a column address buffer 13, a control signal buffer 14, a CLK buffer 15, an address counter 16 and a timing generator 17.
The row address buffer 12 applies an externally applied address signal ADD to the row decoder 2 as a row address signal at a predetermined timing. The column address buffer 13 applies an externally applied address signal ADD to the address counter 16 as a column address signal at a predetermined timing.
The control signal buffer 14 receives an external row address strobe signal /RAS, an external column address strobe signal /CAS, an external write enable signal /WE and an external output enable signal /OE, and applies the same to the timing generator 17. The CLK buffer 15 receives an externally applied clock signal CLK, and applies the same to respective circuits in the chip.
The address counter 16 receives the column address signal-applied from the column address buffer 13 as the start address, and sequentially changes the start address in response to the clock signal CLK. The address counter 16 generates the column address signal which includes two bits A0 and A1, which are applied to the serial/parallel converter circuit 7 and parallel/serial converter circuit 10. Other bits A2-An in this column address signal are applied to the column decoder 5. The timing generator 17 generates various control signals for controlling respective circuits in the chip.
An operation in a random access mode of the DRAM shown in FIGS. 24 and 25 will be described below.
The row decoder 2 selects one of the word lines WL in the memory array 1 in response to the row address signal, and raises its potential to high. Thereby, data are read from the memory cells MC connected to the selected word line WL onto the corresponding bit lines. The read data are sensed and amplified by sense amplifiers SA contained in the sense amplifier group 3, and are held therein.
Thereafter, the column decoder 5 selects one of the bit line groups to activate the corresponding column selecting circuit in response to the bits A2-An in the column address signal, which is applied thereto through the address counter 16. Thereby, the four bit line pairs in the selected bit line group are connected through the column selecting circuit to the four input/output line pairs IO1-IO4, respectively.
In data reading operation, four bits of data on the four bit line pairs in the selected bit line group are applied through the four input/output line pairs IO1-IO4 to the preamplifier 9 for amplification. The four bits of data amplified by the preamplifier 9 are applied to read data buses RDB1-RDB4, respectively. The parallel/serial converter circuit 10 is responsive to the two bits A0 and A1 in the column address signal to apply one of the four bits of data on the read data buses RDB1-RDB4 to the output buffer 11. Consequently, the data is supplied from the output buffer 11 to the input/output terminal I/O.
In data writing operation, the input/output terminal I/O sequentially receives external data. The data are sequentially applied through the input buffer 6 to the serial/parallel converter circuit 7. The serial/parallel converter circuit 7 converts the data into parallel data and applies the same to the write buffer 8. Thereby, the data is applied to each of the four input/output line pairs IO1-IO4. The four data on the input/output line pairs IO1-IO4 are applied through the activated column selecting circuit to the four bit line pairs in the selected bit line group, and are written into the four memory cells MC.
Meanwhile, after the activation of one word line WL, the data held by the sense amplifiers SA contained in the sense amplifier group 3 can be continuously read onto the input/output line pairs IO1-IO4 by sequentially activating the column selecting circuits.
A mode, in which the column selecting circuits are randomly activated in accordance with the externally applied address signals is referred to as a page mode. A mode, in which only the address signal designating the start address is set in the address counter 16, and thereafter, the column selecting circuits are sequentially activated by the address signals generated from the address counter 16, is referred to as a serial mode. Since the sense amplifier group 3 generally holds the data of thousands of bits, the page mode and serial mode enable access at a high speed.
Particularly, in the serial mode, a plurality of data, which are obtained by the activation of one column selecting circuit, may be subjected to the parallel/serial conversion, or a time sharing operation (pipeline control) may be carried out, whereby the speed of serial access is further increased.
FIG. 26 shows a major part of the DRAM shown in FIGS. 24 and 25. In FIG. 25, the bit line group BG1 includes the bit line pairs BL1-BL4, and the bit line group BG2 includes the bit line pairs BL5-BL8. A bit line group BG3 includes bit line pairs BL9-BL12, and a bit line group BG4 includes bit line pairs BL13-BL16.
The column addresses allocated to the bit line pairs BL1-BL16 are designated by Y1, Y2, . . . , Y16, respectively.
The bit line pairs BL1-BL4 in the bit line group BG1 are connected through the column selecting circuit SL1 to the input/output line pairs IO1-IO4, respectively. The bit line pairs BL5-BL8 in the bit line group BG2 are connected through the column selecting circuit SL2 to the input/output line pairs IO1-IO4, respectively. The bit line pairs BL9-BL12 in the bit line group BG3 are connected through the column selecting circuit SL3 to the input/output line pairs IO1-IO4, respectively. The bit line pairs BL13-BL16 in the bit line group BG4 are connected through the column selecting circuit SL4 to the input/output line pairs IO1-IO4, respectively,
As described above, the input/output line pairs IO1-IO4 are common to all the bit line groups. Therefore, simultaneous activation of the multiple column selecting circuits is impossible.
In the serial mode, the start address is set in the address counter 16, and one column selecting circuit corresponding to the start address is activated.
As shown in FIG. 27, if the start address is set at any of Y1-Y4, the column selecting circuit SL1 is first activated. If the start address is set at Y1, the column addresses Y1, Y2, Y3 and Y4 are sequentially accessed, upon activation of the column selecting circuit SL1. If the start address is set at Y2, the column addresses Y2, Y3 and Y4 and are sequentially accessed, upon activation of the column selecting circuit SL1. If the start address is set at Y3, the column addresses Y3 and Y4 are sequentially accessed, upon activation of the column selecting circuit SL1. If the start address is set at Y4, only the column address Y4 is accessed, upon activation of the column selecting circuit SL1.
As described above, the extent which can be accessed without requiring the activation of another column selecting circuit, depends on the start address. In particular, if the start address is set, for instance, at Y4, it is necessary to activate another column selecting circuit in order to access the next column address. This results in a problem that a time period from the activation of the column selecting circuit to the operation of the preamplifier determines the bit rate.
This problem will be described below with reference to waveform diagrams of FIGS. 28 and 29.
FIG. 28 is a timing chart showing an operation when the start address is set at Y1 in the serial mode. FIG. 29 is a timing chart showing an operation when the start address is set at Y4 in the serial mode.
In FIGS. 28 and 29, D1-D12 designate data read onto the bit line pairs BL1-BL12 (see FIGS. 25 and 26), respectively.
When the external row address strobe signal /RAS falls to low, an externally applied address signal ADD is applied to the row decoder 2 as a row address signal AX. Thereby, one of the word lines WL is activated. Thereafter, when the external column address strobe signal /CAS falls to low, an externally applied address signal ADD is applied to the address counter 16 as a column address signal AY. The address counter 16 applies the two bits A0 and A1 in the column address signal AY to the parallel/serial converter circuit 10, and applies the other bits A2-An to the column decoder 5.
As shown in FIG. 28, if the column address signal AY designates the column address Y1, the start address is set at Y1. First, the column decoder 5 raises the column selecting signal CSL1 to high and activates the column selecting circuit SL1. Thereby, the data D1-D4 on the bit line pairs BL1-BL4 are read onto the input/output line pairs IO1-IO4, respectively.
The data D1-D4 are applied through the preamplifier 9 to the read data buses RDB1-RDB4. The address counter 16 sequentially counts up the column address signal AY in response to the clock signal CLK applied from the CLK buffer 15. The parallel/serial converter circuit 10 sequentially selects the data D1-D4 and applies the same to the output buffer 11 in response to the two bits A0 and A1 in the column address signals AY. In this manner, the data D1-D4 are serially supplied from the input/output terminal I/O as output data Dout.
When the column decoder 5 raises the column selecting signal CSL2 to high, the data D5-D8 are read onto the input/output line pairs IO1-IO4 in a similar manner, respectively. The data D5-D8 are applied through the preamplifier 9 to the read data buses RDB1-RDB4, respectively. The address counter 16 sequentially counts up the column address signal AY in response to the clock signal CLK applied from the CLK buffer 15. The parallel/serial converter circuit 10 by sequentially selects the data D5-D8 and applies the same to the output buffer 11 in response to the two bits A0 and A1 in the column address signal AY. Thereby, the data D5-D8 are sent in serial from the input/output terminal I/O as the output data Dout.
In this manner, the data are read in serial from the input/output terminal I/O.
As shown in FIG. 29, if the column address signal AY designates the column address Y4, the start address is set at Y4. Also in this case, the column decoder 5 first raises the column selecting signal CSL1 to high and activates the column selecting circuit SL1. Thereby, the data D1-D4 on the bit Line pairs BL1-BL4 are read onto the input/output line pairs IO1-IO4, respectively.
The data D1-D4 are applied through the preamplifier 9 to the read data buses RDB1-RDB4, in response to the two bits A0 and A1 in the column address signal respectively. The parallel/serial converter circuit 10 AY selects the data D4 and applies the same to the output buffer 11 in response to the two bits A0 and A1 in the column address signal. Thereby, the data D4 is supplied from the input/output terminal I/O as the output data Dout.
When the column decoder 5 raises the column selecting signal CSL2 to high, the data D5-D8 are read onto the input/output line pairs IO1-IO4 in a similar manner, respectively. The data D5-D8 are applied through the preamplifier 9 to the read data buses RDB1-RDB4, respectively. The address counter 16 sequentially counts up the column address signal AY in response to the clock signal CLK applied from the CLK buffer 15. The parallel/serial converter circuit 10 sequentially selects the data D5-D8 to apply the same to the output buffer 11 in response to the two bits A0 and A1 in the column address signal AY. Thereby, the data D5-D8 are sent in serial from the input/output terminal I/O as the output data Dout.
In this case, the column selecting signal CSL2 can be raised to high only after the column selecting signal CSL1 falls to low. In order to prevent simultaneous change of two column selecting signals to the on-state, a margin is required between the fall of the column selecting signal CSL1 and the rise of the column selecting signal CSL2.
As shown in FIG. 28, if the column address signal AY designates the column address Y1, there is no gap between the output data, and thus the bit rate does not decrease. As shown in FIG. 29, however, if the column address signal AY designates the column address Y4, a gap is generated between the data D4 and D5 supplied from the input/output terminal I/O. Thus, there is a data gap when one bit line pair in a certain bit line group and one bit line pair in another bit line group are continuously selected. This causes reduction of the access speed and bit rate.